SOLUTIONS
Solutions Content
Solution:
The art and practice of analog IC layout has not changed significantly in over 30 years. Sure, LVS is near perfect, DRCs cover almost every rule and SDL eliminates Pcell generation; but placement and routing are still manual efforts. Furthermore, the electrical layout constraints (ie. matching, routing capacitance, ground drops, current density, antenna effects), require experts to properly lay out. These constraints, usually in the form of layout notes, are given to the mask designer to follow and then checked by the design engineer for compliance, one iteration at a time. This interactive process sometimes requires time, man-power resources and re-work. What starts out as concurrent design and layout often becomes a serial process as the analog layout begins to lag the circuit design.
Not anymore! Syncira's revolutionary Analog Layout Integrated Synthesis tool solves not only automated placement and routing using a proprietary layout synthesizer, but also integrates an intelligent NetList Analyzer that reliably drives critical device placement and routing, all automatically.
For the first time, a tool offers true concurrent analog design and layout. This is because the Spice circuit netlist used by the circuit designer for simulation is the same one that drives the analog layout. When a schematic is ready for simulation, it can also be submitted for layout. It does not matter if you are an SOC design engineer in a sea of gates, an entry level analog chip design engineer, or an expert analog design engineer, because the NetList Analyzer examines the spice netlist for the critical electrical layout contraints and intelligently directs the layout synthesizer to generated many layout solutions during placement and routing. Cross-Quading, InterLeaving, Side by Side, routing capacitance loading, electro-migration, latchup, antenna effects, and multiple fingers are automatically included in the layout.
In addition, layout utilities unique for this proprietary layout synthesizer have been developed to capitalize on existing legacy layouts, and sorting and selecting among the many layout solutions generated.
Not anymore! Syncira's revolutionary Analog Layout Integrated Synthesis tool solves not only automated placement and routing using a proprietary layout synthesizer, but also integrates an intelligent NetList Analyzer that reliably drives critical device placement and routing, all automatically.
For the first time, a tool offers true concurrent analog design and layout. This is because the Spice circuit netlist used by the circuit designer for simulation is the same one that drives the analog layout. When a schematic is ready for simulation, it can also be submitted for layout. It does not matter if you are an SOC design engineer in a sea of gates, an entry level analog chip design engineer, or an expert analog design engineer, because the NetList Analyzer examines the spice netlist for the critical electrical layout contraints and intelligently directs the layout synthesizer to generated many layout solutions during placement and routing. Cross-Quading, InterLeaving, Side by Side, routing capacitance loading, electro-migration, latchup, antenna effects, and multiple fingers are automatically included in the layout.
In addition, layout utilities unique for this proprietary layout synthesizer have been developed to capitalize on existing legacy layouts, and sorting and selecting among the many layout solutions generated.
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